High speed signal sampler circuits have metastability problems due to having limited time available for resolving a voltage level at a cross coupled node compared with a signal sampler circuit operating at a lower speed. The metastability problem is exacerbated when a high speed sampler circuit is used in a feedback loop to regulate two input voltages to be close to each other, as in case of power supply regulation. Conventional techniques, such as inputting the output of the sampler circuit through a series of metastability hardened flip-flops to synchronize the output increases the response time. Increasing the response time may not be tolerable for regulating the power supply voltage of an integrated circuit. There is a need for addressing these issues and/or other issues associated with the prior art.